Alignment and Registration

The registration of one layer to another is the basis of the 3 dimensional silicon based semiconductor.  Typically one layer needs to be aligned to its contacted layer below by a tolerance of not more than 10% of feature size.  Transparence of the resist and defects on the wafer by the alignment locations are some of the major reasons alignment fails.  The Stepper/Scanner must have its alignment system characterized and optimized for each layer.

Choose us at for any of the following and more:

  • Alignment signal optimization
  • Alignment mark optimization
  • Defect investigation
  • double patterning registration